1. Field of the Invention
The present invention relates to a semiconductor light emitting device. In particular, the present invention relates to a semiconductor light emitting device manufactured by utilizing a technique of stacking a plurality of semiconductor layers on a semiconductor substrate.
2. Description of the Related Art
Methods are known for fabricating a semiconductor light emitting device by stacking a plurality of semiconductor layers on a GaAs substrate, serving as a growth substrate, utilizing an MOCVD (metal organic chemical vapor deposition) method. For example, on a GaAs substrate, an n-type cladding layer, an active layer, a p-type cladding layer, and a p-type current diffusion layer are sequentially deposited. On the opposite surface of the GaAs substrate to the surface on which the n-type cladding layer is formed (that is, on the rear surface of the GaAs substrate), a rear side electrode is formed. A front surface electrode is formed on the p-type current diffusion layer.
The semiconductor light emitting devices as configured above can be utilized as vehicle rear tail lamps, various indicators, backlight sources for mobile devices such as a cellular phone, and the like. Further, as the demands for vehicle headlamps, backlight sources for liquid crystal display devices, general illuminators, and the like have increased, markets for such semiconductor light emitting devices have expanded. In view of this, further improvements in light emission efficiency and reliability of such semiconductor light emitting devices are also demanded.
In order to improve the light emission efficiency and simultaneously decrease the operating voltage, a technique is known in which a plurality of current diffusion layers having different carrier concentrations are stacked. Japanese Patent Application Laid-Open No. 2004-304090 discloses, for example, a technique of stacking three different current diffusion layers with different carrier concentrations. In the same patent document, a first current diffusion layer with the highest carrier concentration is formed on a cladding layer, and a second current diffusion layer with the lowest carrier concentration is formed on the first current diffusion layer. Then, a third current diffusion layer is formed as an uppermost layer. The third current diffusion layer has a carrier concentration lower than that of the first current diffusion layer and higher than that of the second current diffusion layer.
Another known technique is to reduce an operating voltage and power consumption by inserting an intermediate layer between a cladding layer and a current diffusion layer, to relax a lattice mismatch. For example, Japanese Patent Application Laid-Open No. Hei 9-260724 (corresponding to U.S. Pat. No. 5,777,349) discloses a technique in which an AlInAs layer is inserted as an intermediate layer between an AlGaInP cladding layer and a GaP layer.
Further, it is known that the carrier concentration in an active layer is important for improving the light emission efficiency. Japanese Patent Application Laid-Open No. Hei 11-68154 discloses, for example, that it is important in an AlGaInP type semiconductor light emitting device with a high light emission efficiency to control the Si and Zn concentrations in the active layer.
There have been further strong demands for a semiconductor light emitting device to provide a high luminance and have a higher reliability. Specifically, it is required to precisely control the carrier concentration of an active layer in order to obtain a high light emission efficiency and to reduce a forward voltage in order to obtain high reliability.
However, the carrier concentration in the active layer is apt to be adversely affected by impurities migrated (diffused) from the current diffusion layer on a cladding layer. Accordingly, it is difficult to precisely control the carrier concentration in the active layer because of the different amount of impurities diffused from the current diffusion layer device by device due to the variations in growing temperature, growing time, thickness, and the like, of the current diffusion layer.
Furthermore, a forward voltage is also adversely affected by the thickness variation of the semiconductor layer formed on the growing substrate, the diffused amount of impurities, and the like. Accordingly, it is difficult to sufficiently reduce the forward voltage due to the variations in the thickness of the semiconductor layer, the amount of impurities, and the like.